Semiconductor Memory Device with Improved Soft-Error Resistance
1. Field of the Invention
The present invention generally relates to a semiconductor memory device. More particularly, the present invention relates to the memory cell structure of a static semiconductor memory device.
2. Description of the Background Art
As a memory cell used in a static random access memory (SRAM) (hereinafter, referred to as xe2x80x9cSRAM memory cellxe2x80x9d), an SRAM memory cell having a so-called xe2x80x9cCMOS (Complementary Metal Oxide Semiconductor) structurexe2x80x9d is conventionally known in the art. In the SRAM memory cell having the CMOS structure, a P-type MOS (Metal Oxide Semiconductor) transistor is used as a load transistor and N-type MOS transistors are used as a drive transistor and an access transistor.
FIG. 11 is a circuit diagram showing the structure of the conventional SRAM memory cell having the CMOS structure.
Referring to FIG. 11, conventional SRAM memory cell 100 includes a P-type MOS transistor PT1 and an N-type MOS transistor NT1. P-type MOS transistor PT1 is connected between a power supply node 110 for supplying a power supply potential VDD and a storage node NS. N-type MOS transistor NT1 is connected between a ground node 115 for supplying a ground potential GND and storage node NS. Transistors PT1, NT1 have their gates electrically coupled to a common gate line GL1, and form a single inverter.
SRAM memory cell 100 further includes a P-type MOS transistor PT2 and an N-type MOS transistor NT2. P-type MOS transistor PT2 is connected between power supply node 100 and a storage node /NS. N-type MOS transistor NT2 is connected between storage node /NS and ground node 115. Transistors PT2, NT2 have their gates electrically coupled to a common gate line GL2, and form a single inverter.
Storage node NS is connected to gate line GL2, and storage node/NS is connected to gate line GL1. Such two cross-coupled inverters allow the potentials at storage nodes NS, /NS to be set to complementary levels. In other words, the potential at one of storage nodes NS, /NS is set to one of VDD level (hereinafter, sometimes referred to as xe2x80x9cH levelxe2x80x9d) and GND level (hereinafter, sometimes referred to as xe2x80x9cL levelxe2x80x9d), and the potential at the other storage node is set to the other level.
SRAM memory cell 100 further includes N-type MOS transistors AT1, AT2 respectively connected between complementary bit lines BL, /BL and storage nodes NS, /NS. A gate line GLa1 connected to the gate of transistor AT1 and a gate line GLa2 connected to the gate of transistor AT2 are connected to a common word line WL.
In this way, an SRAM memory cell is implemented which uses P-type MOS transistors PT1, PT2 as load transistors, N-type MOS transistors NT1, NT2 as drive transistors, and N-type MOS transistors AT1, AT2 as access transistors. In the SRAM memory cell of FIG. 11, data is written to or read from storage nodes NS, /NS through complementary bit lines BL, /BL during an active (H level) period of word line WL. During an inactive (L level) period of word line WL, data written to storage nodes NS, /NS are stably retained by the two cross-coupled inverters.
Note that, hereinafter, P-type MOS transistors PT1, PT2 are sometimes referred to as load transistors PT1, PT2, N-type MOS transistors NT1, NT2 are sometimes referred to as drive transistors NT1, NT2, and N-type MOS transistors AT1, AT2 are sometimes referred to as access transistors AT1, AT2.
FIG. 12 shows one example of the two-dimensional layout of the SRAM memory cell in FIG. 11. FIG. 12 shows the layout to the level of a first metal wiring layer. The layout of further wiring layers is not shown in FIG. 12.
Referring to FIG. 12, p-type wells 121, 121# and an n-type well 125 are formed at a semiconductor substrate. Drive transistor NT1 and access transistor AT1, which are N-type MOS transistors, are provided on p-type well 121. Load transistors PT1, PT2, which are P-type MOS transistors, are provided on n-type well 125. Access transistor AT2 and drive transistor NT2, which are N-type MOS transistors, are provided on p-type well 121# which is separated from p-type well 121.
More specifically, diffusion layer regions respectively corresponding to drive transistor NT1 and access transistor AT1 are formed at p-type well 121. Diffusion layer regions respectively corresponding to load transistors PT1, PT2 are formed at n-type well 125. Diffusion layer regions corresponding to access transistor AT2 and drive transistor NT2 are formed at p-type well 121#.
Power supply node 110, ground node 115, word lines WL, bit lines BL, /BL and storage nodes NS, /NS are formed in the first metal wiring layer or the like.
Gate lines GL1, GL2, GLa1, GLa2 are formed from a polysilicon layer or the like. In order to implement the connection of FIG. 11, contacts 120 are provided as required between the first metal wiring layer, the diffusion layer regions and a gate line layer.
For example, regarding drive transistor NT1, a source portion of the diffusion layer region corresponding to drive transistor NT1 is electrically coupled to ground node 115 via a contact 120a. A drain portion of the diffusion layer region corresponding to drive transistor NT1 is electrically coupled to storage node NS via a contact 120a. Storage node NS is also electrically coupled to the diffusion layer region corresponding to access transistor AT1 via contact 120a. 
Gate lines GLa1, GLa2 respectively corresponding to access transistors AT1, AT2 are electrically coupled via corresponding contacts 120a to word line WL formed in the first metal wiring layer. Gate line GL1 extends so as to be coupled to the gates of drive transistor NT1 and load transistor PT1. In a region above n-type well 125, gate line GL1 is electrically coupled to storage node /NS via a contact 120b. Contact 120b is provided as a contact capable of simultaneously connecting the gate, the diffusion layer and the first metal wiring layer (xe2x80x9cshared contactxe2x80x9d). Similarly, gate line GL2 extends so as to be coupled to the gates of drive transistor NT2 and load transistor PT2. In a region above n-type well 125, gate line GL2 is electrically coupled to storage node NS via a contact 120b. In general, such gate lines GL1, GL2, GLa1, GLa2 have a silicide structure. In other words, in gate lines GL1, GL2, GLa1, GLa2, a silicide film, a thin metal silicide film (e.g., cobalt silicide), is formed on a polysilicon layer. This enables reduction in resistance of gate lines GL1, GL2, GLa1, GLa2.
However, recent progress of the semiconductor miniaturization technology increasingly reduces the size of the SRAM memory cells. This causes garbled data (inversion of storage data) due to external factors. One of the external factors is a so-called soft error. The soft error is caused by alpha rays that are emitted from a small amount of radioactive substance included in a package. The mechanism of generating a soft error in an SRAM memory cell will now be described with reference to FIG. 11.
Referring back to FIG. 11, it is now assumed that, in the initial state, an L-level potential is stored in storage node NS, an H-level potential is stored in storage node /NS and word line WL is inactive at L level.
If alpha rays are emitted and electrons are excited in the drain portions of the N-type MOS transistors (AT2, NT2) coupled to storage node /NS storing H level, the potential at storage node /NS drops from H level. In such a case, the potential level at storage node /NS would normally restore to H level after a prescribed time because load transistor P2 connected to storage node /NS is ON.
However, if the on-state resistance between the source and the drain of load transistor PT2 is large, the reduced potential at storage node /NS may be propagated through gate line GL1 before restoring to H level. As a result, load transistor PT1 and drive transistor NT1 may be turned ON/OFF in an inverted manner. In other words, load transistor PT1 may be turned ON and drive transistor NT1 may be turned OFF as opposed to the initial data storage state. Such ON/OFF inversion of the transistors inverts the potential at storage node NS from L level to H level, causing erroneous write operation. In order to address such a soft error, it is necessary to reduce the propagation speed of a potential drop at storage node NS or /NS to the gates of drive transistors NT1, NT2 and load transistors PT1, PT2.
For example, one known measure against a soft error is to increase the capacity of the storage nodes. By increasing the capacity of the storage nodes, a potential drop of storage nodes NS, /NS becomes less likely to be caused by electrons generated by alpha rays, thereby preventing data inversion.
However, the capacity of the storage nodes reduces with reduction in memory cell size. On the other hand, if the storage nodes are designed to have an increased capacity in view of a soft error, the cell area is increased and the cell structure becomes more complex. This may cause increased manufacturing costs and reduced yield.
Moreover, reduction in power supply potential VDD facilitates generation of a soft error. Since the operating voltage of the transistors is now increasingly reduced for reduced power consumption, providing measures against a soft error is becoming increasingly important.
It is an object of the present invention to provide a semiconductor memory device including memory cells with improved soft-error resistance without increasing the area and complicating the structure.
In summary, according to one aspect of the present invention, a semiconductor memory device includes a plurality of memory cells for storing data. Each memory cell includes a first inverter section, a second inverter section, a fifth transistor, a sixth transistor, a first gate line, and a second gate line. The first inverter section includes first and second transistors. The first and second transistors are respectively connected between first and second voltages and a first storage node and have opposite conductivity types. The second inverter section includes third and fourth transistors. The third and fourth transistors are respectively connected between the first and second voltages and a second storage node and have opposite conductivity types. The fifth transistor connects a first signal line to the first storage node. The sixth transistor connects a second signal line complementary to the first signal line to the second storage node. The first gate line has a laminated structure of a first metal layer and a first polysilicon layer, and electrically couple gates of the first and second transistors to the second storage node through a contact resistance between the first metal layer and the first polysilicon layer. The second gate line has a laminated structure of a second metal layer and a second polysilicon layer, and electrically couple gates of the third and fourth transistors to the first storage node through a contact resistance between the second metal layer and the second polysilicon layer.
A main advantage of the present invention is that the poly-metal structure of a word line enables the first and second storage nodes to be electrically coupled to the gates of the first and third transistors Goad transistors) through a contact resistance at the interface between a metal layer and a silicon layer. Accordingly, the propagation speed of a potential drop at the first and second storage nodes caused by external factors such as a soft error to the gates of the first and third transistors (load transistors) can be reduced by merely changing the structure of the gate lines. This enables improvement in soft-error resistance of the memory cell without increasing the memory cell area and complicating the memory cell structure.
According to another aspect of the present invention, a semiconductor memory device includes a plurality of memory cells for storing data. Each memory cell includes a first inverter section, a second inverter section, a fifth transistor, a sixth transistor, a first gate line, and a second gate line. The first inverter section includes first and second transistors. The first and second transistors are respectively connected between first and second voltages and a first storage node and have opposite conductivity types. The second inverter section includes third and fourth transistors. The third and fourth transistors are respectively connected between the first and second voltages and a second storage node and have opposite conductivity types. The fifth transistor connects a first signal line to the first storage node. The sixth transistor connects a second signal line complementary to the first signal line to the second storage node. The first gate line is formed from a first silicon layer and a first metal film formed on the first silicon layer, and is electrically coupled to the second storage node. The first silicon layer is coupled to gates of the first and second transistors. The second gate line is formed from a second silicon layer and a second metal film formed on the second silicon layer, and is electrically coupled to the first storage node. The second silicon layer is coupled to gates of the third and fourth transistors. The first gate line has a non-metal film region, a region where the first metal film is not formed, in a part of a region between the second storage node and the first transistor. The second gate line has a non-metal film region, a region where the second metal film is not formed, in a part of a region between the first storage node and the third transistor.
According to the above semiconductor memory device, a non-silicide region (non-metal film region) provided in a word line having a silicide structure increases the electric resistance between the first and second storage nodes and the gates of the first and third transistors load transistors). Accordingly, the propagation speed of a potential drop at the first and second storage nodes caused by external factors such as a soft error to the gates of the first and third transistors (load transistors) can be reduced by merely adjusting a mask pattern for forming a silicide film (metal film). This enables improvement in soft-error resistance of the memory cell without increasing the memory cell area and complicating the memory cell structure.